1. Field of the invention
The present invention relates generally to plasma display panel and more particularly to a method and a circuit arrangement for separating scan line drive such that the scan line is divided into left part and right part and sequentially driven to improve the resolution of the plasma display panel.
2. Description of the prior art
In general, a plasma display panel is comprised of small neon gas discharge tubes arranged most popularly in a 512.times.512 matrix and provides a much brighter picture than the conventional display tube. In such a plasma display panel, the scanning of plasma display panel is carried out sequentially from the first line to the last line of the picture, and thus the only circuit means including logical and drive unit is necessary for controlling scan line drive.
While there is no problem in use of the above-mentioned plasma display panel in case of the size of screen is relatively small, however, as the size of screen grew larger and as the resolution of picture grew higher, it has been exposed following problem.
In a larger screen, the number of dot or pixel of picture has increased and the number of cathode electrode in plasma display panel should be increased as well. Driving of great number of electrodes requires a high speed operation of high scanning frequency, and this will cause flicker phenomena in discharge and deteriorate picture quality. Also, large screen of plasma display panel makes its duty factor small which reduces light ON period of each dot and consequently this will deteriorate the picture quality.
Japanese Patent publication SHO Nos. 58-124523, 58-195812 and 58-195813 disclosed a display panel driving means which have characteristic features of high speed operation and low power consumption. In these patents, when the plasma display panel is driven sequentially, as drivers for row and column designation connected respectively to data line and scan line are comprised of push-pull driver, it can be shared refresh driving mean with column designation driving means as for scan line. These drivers provide simple circuit configuration and offer convenience to make an integrated circuits.
Also, there is disclosed in U.S. Pat. No. 4,366,504 an matrix type picture display panel comprised of a plurality of data line and scan line which are arranged in row and column and luminance cell is disposed at the respective cross point thereof. This prior art is so called precharge type line sequence drive method that is driven commonly by way of precharge in driving matrix of electro-luminescent panel. Thus, such a method give rise to increse of power consumption and to limitation of frame frequency by required precharge driving time. Accordingly, the above-mentioned method has disadvantage that it is not suitable especially for high speed scanning.
For easy reference, there is shown a block diagram which depict the overall construction of a module of plasma display panel in FIG. 1. In FIG. 1, numeral 10 is designated central processing unit (CPU) of main system, which receives data signal that is signal source generated from personal computer or laptop computer, horizontal/vertical sync. signal, clock signal, enable signal, etc. and produces control signal for driving plasma display panel. The data signal D.sub.0 .about.D.sub.n of CPU 10 is supplied to anode driver 80 of display panel 90 via data buffer 20. Also, brightness signal Y generated in CPU 10 is supplied to anode driver 80 via brightness controller 30, and horizontal/vertical sync. signal SYNC from CPU 10 is supplied to clock generator 40 for panel, and the clock signal CLOCK from CPU 10 is supplied to anode timing generator 60.
Besides, clock generator 40 for display panel is connected such that it controls brightness controller 30, and controls vertical syncronization signal of anode timing generator 60 to drive anode driver 80. Also, clock generator 40 is connected such that it controls horizontal sync. signal of cathode timing generator 50 to drive cathode driver 70. Thus, in this circuit, the anode driver 80 drives vertical line of display panel 90 according to vertical sync. of display panel 90 and the cathode driver 70 drives horizontal line of display panel 90 according to horizontal sync. of the panel 90.
In this arrangement, the conventional method of sequential scanning is, as shown in FIG. 2, such that cathode timing generator 50 which receives control signal from clock generator 40 generates control signals for controlling left side and right side cathode driver 71 and 72 as well as clock signal K-CLK for left and right side cathode dirver 71 and
Further, both left and right side cathode driver 71, 72 are comprised of shift registors and connected to display panel 90 through each of switching transistors.
The operation of the circuit of FIG. 2 is appeared in timing diagram of FIG. 3. In FIG. 3, the cathode clock signal (a) generated from cathode timing generator 50 is applied to both left and right side cathode drivers 71, 72. At this time, signal (b) for left side cathode driver 71 is applied to the first line X.sub.0 of display panel 90 through the first switching transistor to initiate scanning. Subsequently, signal (c) for right side cathode driver 72 is applied to the second line X.sub.1 of display panel 90 through the driver 72 and the first switching transistor.
As mentioned above, the control signal is supplied sequentially from cathode timing generator 50 to both left and right side cathode drivers 71, 72 and thus display panel 90 undergoes sequential scanning.
On the other hand, refering to the timing diagram FIG. 3, at one half of the applied frequency both left and right cathode driver 71, 72 will operate, however, the enable time for substantial scanning operation is period to. Thus, as the scan enable time is reduced to one half of real operating frequency, the brightness of display panel is not sufficient in respect of real operating frequency.